The project report must be complete
enough for the marker to be able to understand, compile and simulate your
system without consulting other references. Your well-typed report should
include at least the following items (information provided for each item
must be concise):
Problem description.
State objectives and specifications of the project.
Design solution.
Explain your design methodology in designing the project. For example, explain
the type of the architecture selected (behavioral, dataflow, or structural)
and justify your choice.
Block and timing diagrams. Identify
the project modules according to your modeling. For each module draw an icon
showing all input and output signals. Also, show connections between modules.
Summarize signal information in the form of a table. For each signal, show
its name, mode, type, and any other comments. In addition, any relevant timing
diagrams necessary to understand your project should be carefully drawn.
VHDL source code listing. All
source code must be fully documented:
Include every piece of code used to
develop the project.
Any code that is copied or modified
must be referenced.
Each source file should include a
heading comment that includes the file name, date, author, and the overall
functionality of the modules included in the file in addition to the required
inputs and outputs.
Clear comments are required.
Test procedure.
Clearly explain your procedure for testing the project to ensure its correctness.
(Remember that designing testbenches is an integral part of the project.)
Turn in all code used for testing and include any script either entered directly
from the main simulator window or saved in a command file.
Simulation snapshots.
Snapshots from your simulation output should be included in the report. Be
selective!
Results and discussion.
Briefly comment on your design and its relation to stated specifications.
Summarize errors, pitfalls, and problems encountered while doing the project.
Mention new things learnt from the project.