DIGITAL VLSI SYSTEMS


VHDL LANGUAGE BASICS

 
Example 11 (type bit) with delays  entity/architecture testbench
 stimulus file
waveforms
Example 11 (type std_logic) with delays
  entity/architecture testbench stimulus file
waveforms
Example 13  entity/architecture testbench stimulus file
waveforms
Example 14  entity/architecture testbench stimulus file
waveforms



Example 16  entity/architecture testbench stimulus file
waveforms
Example 21  entity/architecture testbench
waveforms
 

MODELING COMBINATIONAL LOGIC

 
using procedure in a package  package entity/architecutre
 testbench
 waveforms
using function in a package  package entity/architecutre
 testbench
 waveforms