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-- A counter that starts from 0 and increments mod 16 on each rising edge of the clock.
-- This one includes:
--
-- Reset input: A positive reset input resets the counter to zero. The output stays zero 
-- as long as the reset input is '1' and resumes counting on the next clock rising edge 
-- after reset changes to '0'.
--
-- Stop input: A positive stop input stops the counter. The output stays at its current 
-- value forever.
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ENTITY counter IS
   PORT( clk, reset, stop: IN bit;
         count: OUT natural); 
END ENTITY counter;

ARCHITECTURE behav OF counter IS
BEGIN 
   preset: PROCESS IS
     VARIABLE count_value: natural := 0;
   BEGIN
     count <= count_value;
     outer: LOOP
       inner: LOOP
         WAIT UNTIL clk = '1' or stop = '1' or reset = '1';
         EXIT outer WHEN stop = '1';
         EXIT WHEN reset = '1';
         count_value := (count_value + 1) MOD 16; 
         count <= count_value;
       END LOOP inner;
       count_value := 0;
       count <= count_value;
       WAIT UNTIL reset = '0';
     END LOOP outer;
     WAIT;
   END PROCESS preset;
END ARCHITECTURE behav;