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-- A circuit that counts the ones in a vector.
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ENTITY ones IS
   PORT( a: IN std_logic_vector(7 DOWNTO 0);
         b: OUT natural); 
END ENTITY ones;

ARCHITECTURE behav OF ones IS
BEGIN 
  Pones: PROCESS (a) IS
    VARIABLE n,v: natural;
    VARIABLE x: bit;
  BEGIN
    n := a'low; v := 0;
    WHILE n <= a'high LOOP 
      x := a(n);
      n := n + 1;
      NEXT WHEN x = '0';
      v := v + 1;
    END LOOP;
    b <= v;
  END PROCESS Pones;
END ARCHITECTURE behav;