Computer Engineering 465 / Electrical Engineering 543
DIGITAL VLSI
SYSTEMS
Testbench
File
This file contains the VHDL
testbench
code of the "equal_test" circuit.
LIBRARY ieee; -- Include the ieee library
USE ieee.std_logic_1164.ALL; -- Logical naming of the 1164 part
ENTITY equal_test IS -- Entity definition of "equal"
-- Empty port list
END equal_test;
ARCHITECTURE testbench OF equal_test IS -- Architecture for "equal_test"
COMPONENT equal IS -- declare equal as a component
PORT (a,b : IN std_logic; -- Port list
e: OUT std_logic);
END COMPONENT equal;
SIGNAL data_in_1, data_in_2: std_logic; -- Internal signal
SIGNAL data_out: std_logic;
FOR CUT: equal -- Configure which entity and which architecture
USE ENTITY work.equal(equalarch);
BEGIN
CUT: equal -- Instantiate the component
PORT MAP(a => data_in_1, -- Port mapping
b => data_in_2,
e => data_out);
verify: PROCESS IS -- Apply stimulus to CUT
BEGIN
-----------------------------------------------
-- Test case #1 --
-- Inputs: (a = '0' and b = '0') --
-- Expected output: (e = '1') --
-----------------------------------------------
data_in_1 <= '0'; data_in_2 <='0'; WAIT FOR 2 ns;
ASSERT data_out = '1'
REPORT "Test case 1: (a = '0' and b = '0') failed"
SEVERITY warning;
-----------------------------------------------
-- Test case #2 --
-- Inputs: (a = '0' and b = '1') --
-- Expected output: (e = '0') --
-----------------------------------------------
data_in_1 <= '0'; data_in_2 <='1'; WAIT FOR 2 ns;
ASSERT data_out = '0'
REPORT "Test case 2: (a = '0' and b = '1') failed"
SEVERITY warning;
-----------------------------------------------
-- Test case #3 --
-- Inputs: (a = '1' and b = '0') --
-- Expected output: (e = '0') --
-----------------------------------------------
data_in_1 <= '1'; data_in_2 <='0'; WAIT FOR 2 ns;
ASSERT data_out = '0'
REPORT "Test case 3: (a = '1' and b = '0') failed"
SEVERITY warning;
-----------------------------------------------
-- Test case #4 --
-- Inputs: (a = '1 and b = '1') --
-- Expected output: (e = '1') --
-----------------------------------------------
data_in_1 <= '1'; data_in_2 <='1'; WAIT FOR 2 ns;
ASSERT data_out = '1'
REPORT "Test case 4: (a = '1' and b = '1') failed"
SEVERITY warning;
END PROCESS verify;
END ARCHITECTURE testbench;
