Computer Engineering 465 / Electrical Engineering 543
DIGITAL VLSI
SYSTEMS
Top-level
Description File
This file contains the VHDL higher
level code of the "equality-check" circuit.
LIBRARY ieee; -- Include the ieee library
USE ieee.std_logic_1164.ALL; -- Logical naming of the 1164 part
USE work.sub_pkg.ALL; -- Logical naming of the subtract package
ENTITY equal IS -- Entity definition of "equal"
PORT (a, b: IN std_logic; -- Port list
e: OUT std_logic);
END ENTITY equal;
ARCHITECTURE equalarch OF equal IS -- Architecture for "equal"
SIGNAL e_1: std_logic; -- Internal signal
FOR subtract_1: subtract USE ENTITY work.subtract(subtract_arch);
BEGIN
subtract_1: subtract -- Instantiate the component
PORT MAP(a => a, -- Port mapping
b => b,
c => e_1);
e <= NOT e_1; -- Definition for e
END ARCHITECTURE equalarch;
