Introducing Mentor Graphics’ Leonardo

Introduction

The objective of this tutorial is to introduce the Mentor Graphics’ Leonardo tool that is to be used for synthesis of VHDL designs. This documentation describes in detail all the steps required to carry out projects. This involves selecting the technology to be used, running the synthesis flow, and inspecting RTL and technology schematics.

Environment Setup

Creating a VHDL design. First, you must have VHDL files that represent a design that you compiled and simulated to make sure it is free of errors.
Creating a working directory. Create a subdirectory under the project main directory to place the output files from the synthesis process in.

Running the Synthesis Flow

Launching Leonardo and select a license to check out. Double click on the Leonardo icon to launch the software. When asked to select a license to check out, select LeonardoSpectrum level 3.

Setting Leonardo for quick setup. We will follow the quick setup flow. Check Tools => Quick Setup. Then, do the following settings from the Quick Setup Panel at the left portion of the main window:

Set up the working directory. Set the working directory by clicking on the button labeled Working Directory.
Add the VHDL files representing the design. All VHDL design files should be listed in the text window labeled Input. To add a file to the list, press the button labeled Open files. To remove a file, just select it from the list and press delete.
Select target technology. Selecting the target technology (e.g., FPGA or CPLD) is done from the list labeled technology. This list contains all the technology devices supported in the tool.
Set the clock frequency. You can set the Clock Frequency you would like the design to work at from the Constraints area.
Set the optimization effort. You can select the optimization effort from the Optimization Effort. Note that, the higher the optimization effort, the longer the time the synthesis process takes.
Set the output file. The output file name is automatically selected based on the name of the first input file added to the Input list. However, you can change the name if you want.
Check the place and rout option. If you are targeting an FPGA type whose vendor's place and route software is integrated in Leonardo, you can check the Run Integrated Place and Route option to run after the synthesis process. Note that you will not be able to see this option if your screen area setting is less than 1024 by 768 pixels.

Running the flow. After selecting the input files and target technology, the Run Flow button is enabled. To run the flow, press this button.

Monitoring the synthesis process. You can monitor the progress of the synthesis process in the Transcript window at the top right portion of the main window. If there are any errors you will see them there too.

Viewing the process summary file. Click on View the current summary file button to open the summary file. This file contains the following information: the space the design occupies on the chip, delay time, the maximum clock speed it uses (if the design uses any!).

Inspecting RTL, Technology, and Critical Path Schematics

Inspecting RTL schematic. Select Tools => View RTL Schematic or click the View RTL Schematic button.
Inspecting technology schematic. Select Tools => View Gate Level Schematic or click the View Technology Schematic button.
Inspecting critical path schematic. Click the View Critical Path Schematic button.
Invoking the design browser. Select Tools => Design Browser. The design browser is used to browse design’s ports, nets and cells to locate any of them on the schematic. For a design with architecture behav, behav is the name of technology dependent design whereas behav_XRTL is the RTL design.

Quitting Leonardo. To quit, select File => Exit from the main window.

Getting More Help

For more information about quick setup you can:

Press the button labeled Help.
Watch a video tutorial by selecting Help => Video Tutorial.

Return back to the course home page.