Do not, under any circumstances, permit any other student to see any part of your program/lab documentation, and do not permit yourself to see any part of another student's program/lab documentation. In particular, you may not test or debug another student's code, nor may you have another student test or debug your code. (If you can not get code to work, consult your lab TA.) Using another student's code in any form or writing code for use by another student violates the university's academic regulations. In addition, submitted lab documentation should be based only on your own work.
The standard penalty for violating these rules on one part of one lab is to receive a zero for the entire lab.
Cheating, plagiarism and other forms of academic fraud are taken very seriously by both the University and the Department. You should consult http://web.uvic.ca/calendar2004/FACS/UnPr/UARe/PoAcI.html for the UVic policy on academic integrity.
* | Prelab: | 5 marks |
__________ |
* | In-lab demo: |
10 marks |
__________ |
* | Lab report: | 15 marks |
__________ |
* | Total: | 30 marks | __________ |
* | Problem description/specification: | 1 |
__________ |
* | Design solution: | 2 | __________ |
* | Structural diagrams (icons,
signal tables, connection diagrams, and timing diagrams): |
2 |
__________ |
* | Test strategy and testbench
design: |
2 |
__________ |
* | VHDL source code listing and
documentation: |
2 |
__________ |
* | Simulation snapshots: | 2 | __________ |
* | Discussion of results: |
2 |
__________ |
* | Overall organization (including references, etc.), effort, and accuracy: | 2 |
__________ |
* | Total | 15 |
__________ |
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